Frequency synthesizer

ABSTRACT

The invention relates to a circuit for frequency synthesis, comprising: a digital controlled oscillator, comprising (a) a clock generator; an accumulator circuit to which the signal from the clock generator is fed; and a control digit feed circuit for feeding to the digital oscillator a signal representing a control digit; and (b) a phase-locked loop which is connected to the carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter and a controlled oscillator, wherein the carry output terminal is connected to the phase detector. The digital controlled oscillator is preferable adapted to generate a signal representing a remainder, wherein a correction circuit is arranged for deriving a correction signal from the remainder. The correction circuit is connected to a combination circuit connected to one of the inputs of the phase detector or to a combination circuit incorporated in the phase-locked loop. The circuits can also be connected in cascade.

The application relates to a circuit for frequency synthesis.

Such circuits are generally known. Frequency synthesizers are thus knownwhich comprise a digital controlled oscillator followed by a filter.When the digital controlled oscillator is adapted for generating morethan one frequency, the relevant filter must of course be a trackingfilter. Such so-called tracking filters are expensive and bulky.

Such prior art circuits are moreover only suitable for large frequencysteps. Nor are they suitable for integration into a modulator.

The object of the present invention is to provide a circuit forfrequency synthesis wherein the above mentioned drawbacks are avoided.

This object is achieved by such a circuit which is characterized by:

a digital controlled oscillator, comprising:

a clock generator;

an adder circuit to which the signal from the clock generator is fed;and

a control digit feed circuit for feeding a signal representing a controldigit to the adder circuit; and

a phase-locked loop which is connected to the carry output terminal ofthe adder circuit and which is provided with a phase detector, alow-pass filter and a controlled oscillator, wherein the carry outputterminal is connected to the phase detector. It is noted here that inthe literature such a digital oscillator is also known as a fractionalrate multiplier, digital controlled oscillator, or as accumulatorcircuit. The frequency of the output signal, the carry signal, satisfiesthe following formula: ##EQU1## wherein: N_(max) --is the largest numberwhich can occur in the adder circuit;

N_(i) --is the control digit;

f_(sys) --is the system frequency;

f_(carry) --is the frequency of the carry signal.

Although a circuit according to the above mentioned claims can easily beembodied in integrated form and no tracking filter is necessary due tothe use of a PLL, the wave shape is found to be not entirely optimal.This is due to the fact that--as a result of the operation of thedigital controlled oscillator--the frequency of the output signal is notregular.

The adder circuit is adapted to generate a remainder-representingsignal. Preferably arranged is a correction circuit for deriving acorrection signal from this remainder. According to a first embodimentan output terminal of the correction circuit is connected to acombination circuit which is connected to the input terminals of thephase detector.

The results are however improved even more when the correction circuitcomprises three controlled accumulators and a D/A converter.

The very best results are however obtained only when the correctioncircuit comprises N digital controlled accumulator circuits, whereineach of the accumulators is adapted to receive the remainder of thepreceding accumulator and each of the accumulators is connected via aplurality of difference determining circuits equal to its ordernumber--1 to an adder circuit, the output terminal of which is connectedto the D/A converter.

The above described frequency synthesizer is suitable for generating asine-shaped signal, a saw-tooth signal, a square wave signal or othertype of signal of which the frequency is externally controlled, forinstance for generating a signal for use in measuring equipment or inmodulators and/or demodulators.

In such an application it is therefore attractive to integrate themodulation process or the demodulation process in the circuit. It isassumed here that by the term "modulate" in the accompanying claims isalso understood demodulate; both after all comprise making a non-linearcombination of the signal for processing with a carrier wave signal.

The circuit according to the invention can be used in frequency or phasemodulation and even in amplitude modulation. In this latter case acombination is made of two or more phase modulators. It is of coursepossible to use the circuit according to the invention in a combinationof frequency or phase modulation with amplitude modulation.

The invention will be further elucidated hereinbelow with reference tothe annexed drawings, wherein:

FIG. 1 shows a diagram explaining the operation of a digital controlledoscillator;

FIG. 2 shows a phase spectrum of the signal generated by the digitalcontrolled oscillator;

FIG. 3 shows a frequency spectrum of the signal generated by the digitalcontrolled oscillator;

FIG. 4 shows a diagram of a first embodiment of a circuit according tothe invention;

FIG. 5 shows a diagram of a second embodiment of a circuit according tothe invention;

FIG. 6 shows a circuit according to the invention which produces asignal with a better quality through the choice of control digits andratios;

FIG. 7 shows a circuit according to a third embodiment of the invention;

FIG. 8 shows a circuit according to the invention which is adapted forphase or frequency modulation;

FIG. 9 shows another embodiment of a diagram which is suitable for phaseor frequency modulation;

FIG. 10 shows a diagram of a circuit according to the invention adaptedfor phase modulation;

FIG. 11 shows a phaser diagram to elucidate the principle of thecircuits for amplitude modulation shown in FIG. 12;

FIG. 12 shows a diagram of a circuit according to the invention suitablefor amplitude modulation; and

FIG. 13 shows a diagram of a circuit according to another embodimentaccording to the invention, with which multiple modulation is possible.

For an understanding of the present invention it is important tounderstand the operation of a digital controlled oscillator. The circuitand the operation of a digital controlled oscillator is thus firstelucidated with reference to FIG. 1.

The digital controlled oscillator 1 shown in FIG. 1 is formed by aregister 2 to which a clock signal with the frequency f_(sys) issupplied via a clock signal line 3. The register is connected on itsinput side to a digital adder circuit 4, while the likewise paralleloutput terminal of the register is connected to one of the two inputterminals of adder circuit 4. Connected to the other input terminal ofadder circuit 4 is a control digit register circuit 5. The outputterminal of the register is also embodied separately. It is of coursealso possible to vary the content of the control digit register 5 fromoutside. In the wording of the claims the combination of adder circuitand register is referred to as accumulator.

The operation of this control digit circuit is as follows: in the addercircuit 4 the content of the control digit register 5 is added to thecontent of the register prior to the preceding clock cycle. The resultof this addition is fed to the register 2. This addition is hereinperformed modulo a determined number. This determined number willcorrespond to the maximum content of the register, in general thus apower of 2. Thus, for each addition which exceeds this power of two, forinstance 8, a carry signal results which essentially forms the outputsignal of the digital controlled oscillator. Only when in the result ofan addition the maximum content is not reached is no carry signalgenerated. Thus, in the case the dividend is 7 and the maximum contentof the register is 8, a carry signal is generated seven of the eighttimes a clock pulse is supplied.

It will be apparent that the thus obtained output signal is subject toserious phase errors. Expressed in time these phase errors lie in therange between 0 and 1/f_(sys). The starting point here is the situationwhere the reference level lies at a limit of the range over which thephase errors are distributed; it is likewise possible to place thereference point in the middle of this range and to let it extend to bothsides. The maximum phase error is then of course a factor of 2 smaller,but this can be positive as well as negative.

This is all shown in FIG. 2. The output signal is therefore affected bya phase error and it is possible to depict this phase error in thefrequency range. This results in FIG. 3.

In FIG. 3 the rectangular characteristic shows the distribution of thefrequency of the digital oscillator. It can be seen here that thesefrequencies extend between 0 and twice the generator frequency. Littlecan be said however about the distribution hereof. The drawing istherefore limited to a uniform distribution. The object is of course togenerate only the actual target frequency, F_(gen). There are inprinciple three possible ways of doing this:

A) lowering all frequencies except for the desired frequency,

B) suppressing the frequencies around f_(gen) in the direct vicinityhereof; further operation can then take place with a filter,

C) a priori only generating the desired frequency.

The resulting frequency spectra are designated with A respectively B inFIG. 3.

A first embodiment of the invention will now be shown with reference toFIG. 4, which embodiment follows the strategy designated under "A"above.

The circuit is formed by a digital controlled oscillator 8 to which aclock signal is fed via a clock signal line 9 and to which via Nparallel lines 10 a control digit is fed in digital form. The digitalcontrolled oscillator has two output terminals. At a first outputterminal a digital signal becomes available, the frequency of which isthe same as the frequency presented by the control digit.

This signal is fed via a combination circuit 17 to a phase detector 12which forms part of a phase-locked loop 13. The phase-locked loopcomprises a voltage-controlled oscillator 14 and a low-pass filter 15.It is noted here that under voltage-controlled oscillators are alsounderstood current-controlled oscillators. The output signal of thephase detector is fed to the low-pass filter 15, the output signal ofwhich controls the voltage-controlled oscillator 14. The output signalof the voltage-controlled oscillator 14 becomes available at an outputterminal 16 and is also fed to a second input terminal of the phasedetector 12. Further arranged between the phase detector and thelow-pass filter is the analog adder circuit 14a.

The digital controlled oscillator is further provided with a secondoutput terminal at which the remainder of the addition performed by thedigital controlled oscillator is available. This remainder is fed to acorrection circuit 19, the output terminal of which is connected to acombination circuit 17.

The operation of the circuit will be explained hereinbelow.

The digital controlled oscillator acts initially as an adder. The clocksignal 9 coming from a crystal oscillator not shown in the diagram isadded by the digital adder circuit 4 in the digital controlledoscillator 8, wherein, in order to bring about optimum operation of theoscillator, the counting preferably takes place until an "ugly" numberis obtained. By an "ugly" control digit is understood a control digitwhich, when divided by the overflow number, produces a poorly divisiblefraction; in other words, that as few factors as possible occur incommon in both numbers. Reference is otherwise made herein to theformula on page 2. This will result in a ratio between the frequency ofthe output signal of the voltage-controlled oscillator and the clocksignal fed thereto, wherein as few components of the clock signal aspossible are to be found in the output signal, which is of the utmostimportance for further processing of the signal.

The output signal is fed to the phase-locked loop which removes possiblyremaining unwanted frequency components.

This is related to the fact that the output signal of the digitalcontrolled oscillator is a square wave, which, as a result of theoperation of the digital oscillator, is not entirely regular, so thatthis square wave comprises a high percentage of undesired, non-harmoniccomponents which must of course be filtered out. This filtering takesplace by means of a phase-locked loop.

The output signal of the phase-locked loop is therefore substantiallysine-shaped or of other shape without further components.

The correction circuit 19 therefore has as its most important functionto correct the phase of the output signal by using as correction termthe remainder present on the digital controlled oscillator 8. A D/Aconverter 21 is of course necessary for this purpose, since theremainder is a digital form and the phase-locked loop is a circuit withanalog operation.

According to an embodiment not shown in the drawings a divider circuitis arranged between the voltage-controlled oscillator and the phasedetector. The use of the described divider circuit creates thepossibility of reducing the time error. When the divider circuit has adivider M, time resolution can be improved by a factor M. A shiftregister-like circuit is herein used which in fact forms animplementation of the combination circuit 17. The shift register-likeconstruction can be clocked with a multiple of the system frequency orwith the frequency generated by the voltage-controlled oscillator orwith a signal derived from said frequency with a divider. Use can alsobe made of an oscillator of which the system clock is derived from adivider circuit. The resolution is then F_(sys) /M, herein T_(sys)=1/f_(sys).

FIG. 5 shows a second embodiment of the frequency synthesizer accordingto the invention wherein the correction circuit has a differentconfiguration. In the figure only the analog adder circuit 14a isdesignated, while the combination circuit 17 (not shown) can also beused, either in combination or not. This is the configuration accordingto model B in FIG. 3.

The correction circuit 22 according to this second embodiment comprisesa digital accumulator 20 followed by a second digital accumulator 23 anda third digital accumulator 24. In terms of circuitry the accumulatorscorrespond with the digital controlled oscillators. The accumulators aremutually connected herein by means of their remainder terminals. Thecarry terminal of the second accumulator is connected via two delaycircuits 25 to a difference determining circuit 26. The third digitalaccumulator 23 comprises a carry terminal which is connected via a delaycircuit 25 and two difference determining circuits 26 to a digital addercircuit 27. Finally, the carry terminal of the fourth digitalaccumulator 24 is connected to adder circuit 27 via three differencedetermining circuits 26.

The output terminal of adder circuit 27 is connected to D/A converter21.

This circuit further differs from the circuit shown in FIG. 4 in thatthree delay circuits 25 are arranged between the digital controlledoscillator 8 and the phase detector 12 of the phase-locked loop 13.These circuits are of course provided with clock terminals (not shown inthe drawing) for synchronization purposes.

The operation of this circuit differs relative to the circuit shown inFIG. 1 in that the approximation of the correction term supplied to thephase-locked loop is three orders of magnitude better. In the phasedomain this amounts to a drop of 20 dB/decade per accumulator. This willof course result in a better frequency stabilization. It will beapparent that it is possible to change the number of digitalaccumulators in the correction circuit, for instance by only using two.In that case one of the delay circuits 25 connected to the digitalaccumulator 20 is omitted, as is the delay circuit 25 connected to thedigital accumulator 23 and one of the delay circuits connected betweenthe first digital controlled oscillator 8 and the phase detector 12. Ofcourse it is also possible to increase the number of digitalaccumulators to make the approximation more accurate. All theseembodiments fall within the scope of the present invention even thoughthey are not shown in the drawings. The choice of which depends on theaccuracy the output signal is required to satisfy.

It is possible to employ a configuration wherein the correction signalcomprises two parts which each process a part of the remainder and oneof which adds a first correction signal to the signal from the digitaloscillator and the second supplies a second correction signal to thephase-locked loop. (Such a configuration is a combination of the modelsA and B).

Shown in FIG. 6 is another embodiment which falls under the designationC in FIG. 3. Herein two combinations, each of a digital controlledoscillator and a phase-locked loop, are connected in cascade. Each ofthe digital controlled oscillators is provided with a control digitinput terminal. It is of course possible to connect in cascade more thantwo of such combinations. It is of course possible to freely select thedivisions of the digital controlled oscillators which perform thefrequency division. The first digital controlled oscillator 28 changesthe f_(sys) which is presented at its input terminal by a factor asaccording to the formula on page 2, wherein the first PLL only allowsthrough signals located in the direct vicinity of the frequency off_(sys) times the divider of the first digital controlled oscillator. Byagain using the combination of a digital controlled oscillator and aphase-locked loop an improvement in the thus obtained signal is achievedin respect of phase purity and frequency. This provides a large numberof degrees of freedom, wherein it is noted that, particularly whencontrol digits are used which are related to each other as little aspossible, a signal is obtained which is as "clean" as possible.According to this embodiment an oscillator is thus obtained of which thefrequency is freely adjustable and of which the quality of the outputsignal is high.

Shown in FIG. 7 is a third embodiment with which an even better freedomfrom jitter can be obtained.

As in the foregoing embodiments, this circuit comprises a controlledoscillator, which in this embodiment is formed by three blocks 8, 42 and43 and a phase-locked loop which is designated in its entirety by 13.The output terminal of block 8 is also connected to a correction circuit19 which is connected to the phase-locked loop 13. However, in contrastto the foregoing embodiment, correction circuit 19 is connected to adelay circuit 41 which is incorporated in the phase-locked loop andwhich can take the form of a frequency divider. The phase-locked loopalso includes at least one divider (44) arranged between thevoltage-controlled oscillator and the delay circuit. The output terminalof this divider is directly connected to a clock terminal of the delaycircuit.

The digital controlled oscillator is thus formed by three parts. This iscomparable to for instance a prior art 1000-counter; this can be definedas a 10-divider concatenated with a 100-divider. It is thus alsopossible to combine for instance hexadecimal and decimal numbers, suchas a number that consists of two hexadecimal and three decimalpositions. The three decimal positions may be taken together and thenobtain a "MOD 1000" operation. The two hexadecimal positions togetherobtain a "MOD 256" operation.

The digital controlled oscillator is also split in this manner; a block8 which indicates a remainder, a block 43 which indicates a number oftimes π (or 180°) and a block 42 which indicates a number of times π/A.

In order to bring about good concatenation this latter block performs amodulo A operation; A pieces of π/A equals π, i.e. block 43 is increasedby 1 if the modulo operation has sufficient space. In short, 8, 42 and43 together form the digital controlled oscillator.

Block 42 has a content of which the value is always smaller than A. Itcan thus be stated that if the value of the π-signal of block 43 changesat the flank of the clock signal, the remainder in block 42 indicateswhat the error is, expressed in pieces π/A. If now the PLL generates afrequency which is A times as high as the reference signal from block43, this frequency, expressed in time per cycle, thus equals π/A. Theunit of an RF cycle and the remainder has thereby become identical; thisis useful for reducing the error in the time, which was initially amaximum of one system cycle, to one oscillator cycle. Thevoltage-controlled oscillator or VCO will thus generate a much higherfrequency than the system clock signal, which is of course attractive.

The use of the RF clock signal itself is quite simple; the partialremainder in block 42 (the rest of the remainder is in block 8)indicates, expressed in one numeral, the number of full VCO cycles inwhich the reference comes too late relative to the divided down VCOclock signal. By now delaying the divided down VCO clock signal by thesame number of cycles, the remaining error becomes significantlysmaller, i.e. as small as the VCO clock signal.

The remaining remainder in block 8 now indicates in a fraction of the RFcycle that there is still a residual error. The jitter caused by thiserror can be decreased with an integrator or jitter shaper 46 and canthen be combined in the synchronization circuit 47 with the signal fromblock 42 and be added to the delay circuit 41. The jitter shaper 46 thusensures that the maximum phase error of one VCO cycle can be suppressedusing the averaging of the phase error through time. This is animportant suppression function of the PLL.

The use of a variable A for the modulo operation and the dividingoperation results in an additional degree of freedom which can be chosenby causing the digital oscillator to generate an "ugly" frequency. Anexample: say that the VCO is supposed to generate a frequency of 320.1MHz and that the applied system frequency is 20 MHz. It is thenextremely irritating to have A equal for instance 64 and to have togenerate about 5 MHz (320/64) in the digital oscillator. The ratio of 5to 20 MHz is then too much of a whole number, so that rather a lot oflow frequency jitter remains. Instead we choose for instance 54 for A,so that we must generate 320.1/54 equals 5.92 MHz. This produces muchmore high frequency jitter which is much easier to eliminate.

It will be apparent that by using a division by A in the phase-lockedloop 13 as well as in the digital part of the oscillator a samplingprocess is supplied at another frequency, which of course has afavourable effect on the stability and thus on freedom from jitter.

In accordance with a non-essential but attractive embodiment, a low-passfilter 45 is connected between the phase detector and thevoltage-controlled oscillator, as is typical in phase-locked loops.

The above embodiments are essentially suitable for generating a signalwith a constant frequency. It is of course possible to use the circuitsfor generating modulated signals.

An embodiment hereof is shown in FIG. 8. A signal representing thecarrier wave frequency is herein supplied to a digital adder circuit 32via the connection 29 and the modulating frequency or the digital signalrepresenting the modulating phase is supplied via a connection 30. Thetwo signals are added together in the adder circuit 32 and fed to thedigital controlled oscillator 8 as control digit. It will be apparentwithout much explanation that this circuit can be used to generate afrequency-modulated signal or a phase-modulated signal. With the circuitthe phase and the frequency of the generated signal can be extremelyaccurate and are only limited by the technology used.

In the embodiment shown in FIG. 9 an adder circuit 35 is arrangedbetween the digital controlled oscillator 8 and the phase-locked loop13. In this adder circuit the digital controlled oscillator 8 is used togenerate the carrier wave signal in digital form, wherein the modulatingsignal supplied via the connection 34 is added to the carrier wavesignal in adder 35 and subsequently fed to the phase-locked loop 13.This circuit can also be used for both phase and frequency modulation.

FIG. 10 shows an embodiment wherein the modulating signal 34 is suppliedto a D/A converter 36 and the signal is subsequently used in analog formfor addition to the signal circulating in the phase-locked loop 13. Useis herein made of an adder circuit 37 incorporated in the phase-lockedloop 13. It will be apparent that this latter embodiment can only beused for phase modulation. It is however possible to add the signal toother positions in the phase-locked loop, for instance to the signalbetween voltage-controlled oscillator 14 and phase detector 12.

The above described embodiments relate to phase or frequency modulationof a carrier wave. It is possible to produce amplitude modulated signalsby combining phase modulated signals.

This will be clarified with reference to FIG. 11, wherein phasers areshown which each represent a phase-modulated signal and wherein thephase of both signals is opposed and which, when added together, resultin an amplitude-modulated signal. When this is applied in practice thereresults for instance a circuit as shown in FIG. 12. Use is herein madeof the phase modulation circuit shown in FIG. 9, wherein two suchcircuits are arranged which are each supplied with a modulating signalin opposed phase.

The digital controlled oscillator of both circuits can of course becombined and it is necessary to add together the output signal of thetwo circuits. Use is herein made of an analog adder circuit 38. This canbe formed for instance by an adder circuit provided with resistors. Thisis however not a particularly attractive option, since resistors aredifficult to embody in integrated form and they have a high dissipation,which is less desirable particularly in battery-powered appliances. Itis further possible to make use of a transformer, which is alsodifficult to implement in integrated form and which has a number oflimitations in the frequency range. Another possibility is to make useof so-called patch radiators, particularly when using high frequencies.The use of three or more phase modulators to generate anamplitude-modulated signal has the advantage of ensuring that amplitude0 can be generated. When two phase-modulated signals with differingamplitudes are added together, the amplitude of the resulting signal cannever be made 0.

Finally, FIG. 13 shows an embodiment of a circuit for generatingmodulated signals which is suitable for generating signals which arephase- or frequency-modulated and amplitude-modulated. Use is madeherein of a so-called pre-modulation filter which derives signals fromthe modulating signal supplied to pre-modulation filter 40 via terminal39, which signals are suitable for frequency modulation and phasemodulation, wherein the phase modulating signals can be used foramplitude modulation. This circuit corresponds with the circuit shown inFIG. 12 with the exception of the use of a band-pass filter 41 which isused in this embodiment because the thus modulated signal is convertedin frequency. The band-pass filter is necessary to prevent themodulation from being influenced by the conversion.

For a specific application methods A, B and C can be used both alone andin combination. The degree to which a method is used depends on theavailable technology and the set requirements. The correct combinationof methods as well as the contribution of the method can be found bymeans of an optimization procedure.

It will be apparent that various modifications can be made to thecircuit according to the present invention without deviating from theinvention.

We claim:
 1. A circuit, including one or more circuits for frequencysynthesis, at least one of said circuits for frequency synthesiscomprising:a first controlled oscillator which is digitally controlledand adapted to generate a signal representing a remainder, comprising:aclock generator; an accumulator circuit to which the signal from theclock generator is fed; and a control digit feed circuit for feeding tothe accumulator circuit a signal representing a control digit; aphase-locked loop which is connected, via a combination circuit, to acarry output terminal of the accumulator circuit and which is providedwith a phase detector, a low-pass filter incorporated in thephase-locked loop after the phase detector, and a second controlledoscillator incorporated in the phase-locked loop after the low passfilter and before the phase detector, wherein the carry output terminalis connected to the phase detector via said combination circuit; and acorrection circuit for deriving a correction signal from the signalrepresenting a remainder characterized in that an output terminal of thecorrection circuit is connected to said combination circuit which isconnected to an input terminal of the phase detector.
 2. Circuit asclaimed in claim 1, characterized in that the output of the correctioncircuit is connected to a D/A-converter, and the output of theD/A-converter is also connected to an adder circuit (14a) incorporatedin the PLL after the phase detector.
 3. Circuit as claimed in claim 2,characterized in that the correction circuit comprises N accumulatorcircuits, wherein the first of said N accumulator circuits is adapted toreceive said signal representing a remainder, and each of the remainingN accumulator circuits after the first is adapted to receive a remainderof the preceding accumulator circuit in the correction circuit and eachof the N accumulator circuits is connected to a second adder circuit viaa plurality of difference determining circuits equal to an order numberof the accumulator circuit in the correction circuit minus
 1. 4. Circuitas claimed in claim 3, characterized in that a divider circuit isarranged between the second controlled oscillator and the phasedetector.
 5. Circuit as claimed in claim 4, characterized by a cascadecircuit of combinations of at least two of said first controlledoscillator and at least two of said phase-locked loop.
 6. Circuit asclaimed in claim 1, characterized in that the correction circuit isconnected to at least one delay circuit incorporated in the PLL. 7.Circuit as claimed in claim 6, characterized in that at least onedivider is arranged between the second controlled oscillator and thedelay circuit and that the output terminal of the divider is directlyconnected to a clock terminal of the delay circuit.
 8. Circuit asclaimed in claim 7, characterized in that at least one modulo divider isarranged at the output terminal of the accumulator circuit and that acarry signal of the modulo divider is also fed to the correctioncircuit.
 9. Circuit as claimed in claim 8, characterized in that theoutput terminal of the modulo divider is connected to a second secondmodulo divider and that the carry output signal of the modulo divider isfed to the phase detector of the PLL.
 10. The circuit as claimed inclaim 1, characterized in that a divider circuit is arranged between thesecond controlled oscillator and the phase detector.
 11. The circuit asclaimed in claim 1, characterized by a cascade circuit of combinationsof at least two of said first controlled oscillator and at least two ofsaid phase-locked loop.
 12. Circuit for frequency synthesis,comprising:a first controlled oscillator which is digitally controlledand adapted to generate a signal representing a remainder, comprising:aclock generator; an accumulator circuit to which a signal from the clockgenerator is fed; and a control digit feed circuit for feeding to theaccumulator circuit a signal representing a control digit; aphase-locked loop which is connected, via one or more delay circuits, toa carry output terminal of the accumulator circuit and which is providedwith a phase detector, a low-pass filter incorporated in thephase-locked loop after the phase detector, and a second controlledoscillator incorporated in the phase-locked loop after the low-passfilter and before the phase detector, wherein the carry output terminalis connected to the phase detector via said one or more delay circuits;and a correction circuit for deriving a correction signal from thesignal representing a remainder, comprising:N accumulator circuits,wherein the first of said N accumulator circuits is adapted to receivesaid signal representing a remainder, and each of the N accumulatorcircuits after the first is adapted to receive a remainder of thepreceding accumulator circuit in the correction circuit, and each of theN accumulator circuits is connected to an adder circuit via a pluralityof difference determining circuits equal to an order number of theaccumulator circuit in the correction circuit minus 1; and a D/Aconverter connected to an output of said adder circuit; characterized inthat an output terminal of the D/A converter of said correction circuitis connected to a second adder circuit (14a) incorporated in the PLLafter the phase detector.